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data sheet rev. 1. 0 1 / march 2012 ZSPM9000 ultra - compact, high - performance drmos device
zs pm9000 ultra - compact, high - performance drmos device ? 201 2 zentrum mikroelektronik dresden ag rev.1.0 1 all rights reserved. the material c o ntained herein may n ot be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. brief description the ZSPM9000 drmos is a fully optimized, ultra - compact, integrated mosfet plus driver power - stage solution for high - current, high - frequency, syn chronous buck dc - dc applications. the device incorporates a driver ic, two power mosfets, and a bootstrap schottky diode in a thermally enhanced, ultra - compact 6mmx6mm pqfn40 package. with an integrated approach, the ZSPM9000s com - plete switching power st age is optimized for driver and mosfet dynamic performance, system induc - tance, and power mosfet r ds(on) . it uses innova - tive high - performance mosfet technology, which dramatically reduces switch ringing, eliminating the snubber circuit in most buck conver ter applications. an innovative driver ic with reduced dead times and propagation delays further enhances performance. an internal 12v to 5v linear regulator enables the ZSPM9000 to operate from a single 12v supply. a thermal warning function (thwn) warns of potential over - temperature situ ations. the ZSPM9000 also incor porates features such as skip mode (smod) for improved light - load efficiency and a tri - state 3.3v pulse - width modulation (pwm) input for compatibility with a wide range of pwm controllers. th e ZSPM9000 drmos is ideally compatible with zmdis zspm1000, a leading - edge configurable dig - ital power - management system controller for non - isolated point - of - load (pol) supplies. features ? based on the intel? 4.0 drmos standard ? internal 12v to 5v linear re gulator (ldo) ? high - current handling: up to 50 a ? h igh - performance copper - clip package ? tri - s tate 3.3 v pwm input driver ? skip mode (low - side gate turn off) input (smod#) ? w arning flag for over - temperature conditions ? driver output disable function (disb# pin) ? int ernal pull - up and pull - down for smod# and disb# inputs, respectively ? i ntegrated schottky d iode technology in the low - side mosfet ? integrated bootstrap schottky diode ? adaptive gate drive timing for shoot - through protection ? under - voltage lockout (uvlo) ? optimi zed for switching frequencies up to 1mhz be n efits ? fully optimized system efficiency: >93% peak ? clean switching waveforms with minimal ringing ? 72% space - saving compared to conventional discrete solutions ? ideally compatible with zmdis zspm1000 true digita l pwm controller available support ? zspm8000 - kit: e valuation k it combined for the ZSPM9000 and zspm1000 physical characteristics ? operation t emperature : - 40 c to + 1 25 c ? v in : 8v to 15v (typical 12 v) ? i out : 40a ( average ), 50a ( maximu m) ? low - profile smd package: 6 mm x6mm pqfn 40 ? zmdi green packaging and rohs compliant typical applicatio n
zs pm9000 ultra - compact, high - performance drmos device ? 201 2 zentrum mikroelektronik dresden ag rev. 1.01 all rights reserved. the material c o ntained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the c opyright owner. typical applications ? telecom switches ? servers and storage ? desktop computers ? workstations ? high - performance gaming motherboards ? base stations ? network routers ? industrial applications zs pm 9000 block diagram ordering information product sales code description package ZSPM9000 a i1r ZSPM9000 lead - free pqfn40 temperature range: - 40c to +125c reel zspm 8000 - kit integrated e valuation k it for ZSPM9000 and zspm1000 kit sales and further information www.zmdi.com spm@zmdi.com zentrum mikroelektronik dresden ag grenzstrasse 28 01109 d resden germany zmd america, inc. 1525 mccarthy blvd., #212 milpitas, ca 95035 - 7453 usa zentrum mikroelektronik dresden ag, japan office 2nd floor, shinbashi tokyu bldg. 4 - 21 - 3, shinbashi, minato - ku tokyo, 105 - 0004 japan zmd far east, ltd. 3f, no. 51, sec. 2, keelung road 11052 taipei taiwan zentrum mikroelektronik dresden ag, korean office posco centre building west tower, 11th floor 892 daechi, 4 - dong, kangnam - gu seoul, 135 - 777 korea phone +49.351.8822.7.776 fax +49.351.8822.8.7776 phone + 855 - ask - zmdi ( + 855 . 275 . 9634) phone +81.3.6895.7410 fax +81.3.6895.7301 phone +886.2.2377.8189 fax +886.2.2377.8199 phone +82.2.559.0660 fax +82.2.559.0700 disclaimer : this information applies to a product under development. its characteristics and specifications are subject to change without notice. zentrum mikroelektronik dresden ag (zmd ag) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. the information furnished hereby is believed to be true and accurate. however, under no circumstances shall zmd ag be liable to any customer, licensee, or any other third party for any special, indirect, incidenta l, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, o r use of this technical data. zmd ag hereby expressly disclaims any liability of zmd ag to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of zmd ag for an y damages in c onnection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability , or otherwise. v d r v v c i n g h d b o o t g l v c i n 5 v l d o t e m p s e n s e 3 0 k 3 0 k g l l o g i c 1 0 a 1 0 a d i s b # p w m t h w n # v c i n v i n u v l o v c c u v l o c g n d s m o d # p g n d p h a s e v i n b o o t v c i n r u p _ p w m r d n _ p w m ( q 1 ) h s p o w e r m o s f e t ( q 2 ) l s p o w e r m o s f e t g h l o g i c l e v e l s h i f t d e a d t i m e c o n t r o l v s w h g l g h i n p u t t r i - s t a t e l o g i c
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 4 of 27 contents list of figures ................................ ................................ ................................ ................................ ............................. 4 list of tables ................................ ................................ ................................ ................................ ............................... 5 1 ic characteristics ................................ ................................ ................................ ................................ ................ 6 1.1. absolute maximum ratings ................................ ................................ ................................ .......................... 6 1.2. recommended operating conditions ................................ ................................ ................................ .......... 7 1.3. electrical parameters ................................ ................................ ................................ ................................ .... 7 1.4. typical performance characteristics ................................ ................................ ................................ .......... 10 2 functional description ................................ ................................ ................................ ................................ ....... 13 2.1. vdrv and disable (disb#) ................................ ................................ ................................ ........................ 14 2.2. thermal warning flag (thwn#) ................................ ................................ ................................ ................ 15 2.3. tri - state pwm input ................................ ................................ ................................ ................................ .... 15 2.4. adaptive gate drive circ uit ................................ ................................ ................................ ........................ 16 2.5. skip mode (smod#) ................................ ................................ ................................ ................................ ... 17 2.6. pwm ................................ ................................ ................................ ................................ ........................... 19 3 application design ................................ ................................ ................................ ................................ ............. 20 3.1. 5v linear regulator capacitor selection ................................ ................................ ................................ ... 20 3.2. boot strap circuit ................................ ................................ ................................ ................................ ......... 20 3.3. power loss and efficiency testing procedures ................................ ................................ ......................... 20 4 pin configuration and package ................................ ................................ ................................ ......................... 22 4.1. available packages ................................ ................................ ................................ ................................ .... 22 4.2. pin description ................................ ................................ ................................ ................................ ............ 23 4.3. package dimensions ................................ ................................ ................................ ................................ .. 24 5 circuit board layout considerations ................................ ................................ ................................ ................. 25 6 ordering information ................................ ................................ ................................ ................................ .......... 27 7 related documents ................................ ................................ ................................ ................................ ........... 27 8 doc ument revision history ................................ ................................ ................................ ............................... 27 list of figures figure 1.1 safe operating area ................................ ................................ ................................ ............................ 10 figure 1.2 module power loss vs. output current ................................ ................................ ............................... 10 figure 1.3 power loss vs. switching frequency ................................ ................................ ................................ .. 10 figure 1.4 power loss vs. input voltage ................................ ................................ ................................ .............. 10 figure 1.5 power loss vs. driver supply voltage ................................ ................................ ................................ . 10 figure 1.6 power loss vs. output voltage ................................ ................................ ................................ ........... 10 figure 1.7 power loss vs. output inductance ................................ ................................ ................................ ...... 11 figure 1 .8 driver supply current vs. frequency ................................ ................................ ................................ ... 11 figure 1.9 driver supply current vs. driver supply voltage ................................ ................................ ................ 11 figure 1.10 driver supply current vs. output current ................................ ................................ ............................ 11 figure 1.11 pwm thresholds vs. driver supply voltage ................................ ................................ ........................ 11 figure 1.12 pwm thresholds vs. temperature ................................ ................................ ................................ ...... 11 figure 1.13 smod# thresholds vs. driver supply voltage ................................ ................................ ................... 12 figure 1.14 smod# thresholds vs. temperature ................................ ................................ ................................ .. 12 figure 1.15 smod# pull - up current vs. temperature ................................ ................................ ........................... 12
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 5 of 27 figure 1.16 disable thresholds vs. driver supply voltage ................................ ................................ ..................... 12 figure 1.17 disable thresholds vs. temperature ................................ ................................ ................................ ... 12 figure 1.18 disable pull - down current vs. temperature ................................ ................................ ....................... 12 figure 2.1 typical application circuit with pwm control ................................ ................................ ...................... 13 figure 2.2 ZSPM9000 block diagram ................................ ................................ ................................ ................... 14 figure 2.3 thwn# op eration ................................ ................................ ................................ ............................... 15 figure 2.4 pwm and tri - state timing diagram ................................ ................................ ................................ .... 16 figure 2.5 smod# timing diagram ................................ ................................ ................................ ...................... 18 figure 2.6 pwm timing ................................ ................................ ................................ ................................ ........ 19 figure 3.1 power loss measureme nt block diagram ................................ ................................ ........................... 21 figure 4.1 pin - out pqfn40 package ................................ ................................ ................................ .................... 22 figure 4.2 pqfn40 physical dimensions and recommended footprint ................................ ............................. 24 figure 5.1 pcb layout example ................................ ................................ ................................ ........................... 26 list of tables table 2.1 uvlo and disable logic ................................ ................................ ................................ ...................... 14 table 2.2 smod# logic ................................ ................................ ................................ ................................ ....... 17
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 6 of 27 1 ic c haracteristics 1.1. absolute maximum ratings the absolute ma ximum ratings are stress ratings only. the device might not function or be operable above the recommended operating conditions. stresses exceeding the absolute maximum ratings might also damage the device. in addition, extended exposure to stresses above t he recommended operating conditions might affect device reliability. zmdi does not recommend designing to the absolute maximum ratings. parameter symbol conditions min max units maximum voltage to cgnd C vci n, d isb#, pwm, smod#, gl, thwn # pins - 0.3 6.0 v maximum voltage to pgnd or cgnd C vin pin - 0.3 25.0 v maximum voltage to pgnd or cgnd C vdrv pin 16.0 v maximum voltage to vswh or phase C boot, gh pins - 0.3 6.0 v maximum voltage to cgnd C boot, phase, gh pins - 0.3 25.0 v maximum vol tage to cgnd/pgnd C vswh pin dc o nly - 0.3 25 .0 v maximum voltage to pgnd C vswh pin < 20ns - 8.0 25 .0 v maximum voltage to vcin C boot pin 22.0 v maximum sink current C thwn# pin i thwn# - 0.1 7.0 ma maximum average output current 1) i o(av) f sw =350khz, v in =12v, v o =1.0v 45 a f sw =1mhz, v in =12v, v o =1.0v 42 a junction - to - pcb thermal resistance jpcb 3.5 c/w ambient temperature range t a mb - 40 +125 c maximum junction temperature t jmax +150 c st orage temperature range t s tor - 55 +150 c electrostatic discharge protection esd human body model, jesd22 - a114 2000 v charged device model, jesd22 - c101 1000 v 1) i o(av) is rated using drmos e valuation b oard, t a = 25c, natural convection cooling. this rating is limited by the peak drmos temperature, t jmax = 150c, and varies depending on operating conditions, pcb layout , and pcb board to ambient thermal resistance.
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 7 of 27 1.2. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recom - mended operating conditions are specified to ensure optimal performance to the datasheet specifications. zmdi does not recommend exceeding them or designing to the absolute maximum ratings. parameter sym bol conditions min typ max units gate drive circuit supply voltage v d rv 8 12 15 v output stage supply voltage v i n 3 12 15 v 1.3. electrical parameters typical values are v in = 12v, v d rv = 12v, and t a = +25c unless otherwise noted. parameter symbol condi tions min typ max units basic operation quiescent current i q i q =i vdrv , pwm=low or high or f loat 2 5 ma internal 5v linear regulator input current i vdrv 8v zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 8 of 27 parameter symbol condi tions min typ max units disb# input high - level input voltage v ih_disb # 2 v low - level input voltage v il_disb # 0.8 v pull - down current i pld 10 a propagation delay disb# , gl transition from high to low t pd_disbl pwm=gnd , lse= 1 25 ns propagation delay disb# , gl transition from low to high t pd_disbh pwm=gnd , lse= 1 25 ns smod# input high - level input voltage v ih_smod # 2 v low - level input voltage v il_smod # 0.8 v pull - up current i plu 10 a propagation delay smod# , gl transition from high to low t pd_slgll pwm=gnd , disb#= 1 10 ns propagation delay smod # , gl transition from low to high t pd_shglh pwm=gnd , disb#= 1 10 ns thermal warning flag activation temperature t act 150 c reset temperature t rst 135 c pull - down resistance r thwn i pld =5ma 30 250ns timeout circuit timeout delay between gh transition from high to low and gl transition f rom low to high t d_timeout vswh = 0v 250 ns
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 9 of 27 parameter symbol condi tions min typ max units high - side driver output impedance, sourcing r source_gh source current=100ma 1 output impedance, sinking r s ink_gh sink current=100ma 0.8 rise time for gh=10% to 90% t r_gh 6 ns fall time for gh=90% to 10% t f_gh 5 ns ls to hs deadband time : gl g oing low to gh g oing high, 1v gl to 10 % gh t d_deadon 10 ns pwm low propagation delay : pwm g oing low to gh g oing low, v il_pwm to 90% gh t pd_plghl 16 30 ns pwm high propagation delay with smod# held low : pwm g oing high to gh g oing high, v ih_pwm to 10% gh t pd_phghh smod# = low 30 ns propagation delay exiting tri - s tate : pwm (from tri - s tate) g oing high to gh g oing high, v ih_pwm to 10% gh t pd_tsghh 30 ns low - side driver output impedance, sourcing r source_gl source current=100ma 1 output impedance, sinking r sink_gl sink current=100ma 0.5 rise time for gl = 10% to 90% t r_gl 20 ns fall time for gl = 90% to 10% t f_gl 13 ns hs to ls deadband time : sw going low to gl going high, 2.2v sw to 10% gl t d_deadoff 12 ns pwm - high propagation d elay : pwm going high to gl going low, v ih_pwm to 90% gl t pd_phgll 9 25 ns propagation delay exiting tri - s tate: pwm (from tri - s tate) going low to gl going high, v il_pwm to 10% gl t pd_tsglh 20 ns boot diode forward - voltage drop v f i f =10ma 0.35 v breakdown voltage v r i r =1ma 22 v
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 10 of 27 1.4. typical performance characteristics test c onditions: v in =12v, v out =1.0v, v c in =5v, v drv =5v, l out =320nh, t a mb =25c, and natural convection cool - ing, unless otherwise specified . figure 1 . 1 safe operating area figure 1 . 2 module power loss vs. output current figure 1 . 3 power loss vs. switching frequency figure 1 . 4 power loss vs. input voltage figure 1 . 5 powe r loss vs. driver supply voltage figure 1 . 6 power loss vs. output voltage
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 11 of 27 figure 1 . 7 power loss vs. o utput inductance figure 1 . 8 driver supply current vs. frequency figure 1 . 9 driver supply current vs. driver supply voltage figure 1 . 10 driver supply current vs. output current . figure 1 . 11 pwm thresh olds vs. driver supply voltage figure 1 . 12 pwm thresholds vs. temperature 0.0 0.5 1.0 1.5 2.0 2.5 3.0 4.80 4.90 5.00 5.10 5.20 pwm threshold voltage (v) driver supply voltage (v) v il_pwm v tri_lo v tri_hi v ih_pwm v hiz_pwm 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -50 -25 0 25 50 75 100 125 150 pwm threshold voltage (v) temperature ( o c) v il_pwm v tri_lo v tri_hi v ih_pwm v cin = 5v
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 12 of 27 figure 1 . 13 smod# thresholds vs. driver supply voltage figure 1 . 14 smod# thresholds vs. temperature figure 1 . 15 smod# pull - up current vs. temperature figure 1 . 16 disable thresholds vs. driver supply voltage figure 1 . 17 disable thresholds vs. temperature figure 1 . 18 disable pull - down current vs. temperature 1.2 1.4 1.6 1.8 2.0 2.2 4.80 4.90 5.00 5.10 5.20 smod # threshold voltage (v) driver supply voltage (v) v il_smod# v ih_smod# t a = 25 o c 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 -50 -25 0 25 50 75 100 125 150 smod# threshold voltage (v) temperature ( o c) v il_smod# v ih_smod# v cin = 5v -12.0 -11.5 -11.0 -10.5 -10.0 -9.5 -9.0 -50 -25 0 25 50 75 100 125 150 smod# pull - up current (a) temperature ( o c) 1.2 1.4 1.6 1.8 2.0 2.2 4.80 4.90 5.00 5.10 5.20 disb# threshold voltage (v) driver supply voltage (v) v il_disb# v ih_disb# t a = 25 o c 1.40 1.50 1.60 1.70 1.80 1.90 2.00 -50 -25 0 25 50 75 100 125 150 disb # threshold voltage (v) temperature ( o c) v il_disb# v ih_disb# v cin = 5v 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 -50 -25 0 25 50 75 100 125 150 disb# pull - down current (a) temperature ( o c)
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 13 of 27 2 functional description th e ZSPM9000 is a driver - plus - fet module optimized for the synchronous buck converter topology. a single pwm input signal is all that is required to properly drive the high - side and the low - side mosfets. it is capable of driving speeds up to 1mhz. figure 2 . 1 typical application circuit with pwm control v d r v v c i n h d r v d b o o t l d r v v c i n p w m d i s b # s m o d # p g n d p h a s e v i n b o o t v s w h ( q 1 ) h s p o w e r m o s f e t ( q 2 ) l s p o w e r m o s f e t z s p m 9 0 0 0 c g n d 5 v l i n e a r r e g u l a t o r t h w n # t e m p s e n s e c g n d c v i n p w m c o n t r o l v d r v = 8 v t o 1 4 v v i n = 3 v t o 1 4 v c v d r v c v c i n v c i n v o u t c b o o t e n a b l e d d i s a b l e d o n o f f c o n t r o l l o u t c o u t
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 14 of 27 figure 2 . 2 ZSPM9000 block diagram 2.1. vdrv and disable (disb#) the vdrv pin is monitored by an under - voltage lockout (uvlo) circuit. when vdrv rises above ~7.5v, the driver is enabled. when vdrv falls below ~7.0v, the driver is disabled (gh , gl= 0 ; see figure 2 . 2 and section 4.2 ). the driver can also be disabled by pulling the disb# pin low (disb# < v il_disb # ), which holds both gl and gh low regardless of the pwm input state. the driver can be enabled by raising the disb# pin voltage high (disb# > v ih_disb # ). table 2 . 1 uvlo and disable logic note: disb# internal pull - down current source is 10 a (typical) . uvlo disb# driver state 0 x disabled (g h =0 , gl=0) 1 0 disabled (g h =0 , gl=0) 1 1 enabled (see table 2 . 2 ) 1 open disabled (g h =0 , gl=0) v d r v v c i n g h d b o o t g l v c i n 5 v l d o t e m p s e n s e 3 0 k 3 0 k g l l o g i c 1 0 a 1 0 a d i s b # p w m t h w n # v c i n v i n u v l o v c c u v l o c g n d s m o d # p g n d p h a s e v i n b o o t v c i n r u p _ p w m r d n _ p w m ( q 1 ) h s p o w e r m o s f e t ( q 2 ) l s p o w e r m o s f e t g h l o g i c l e v e l s h i f t d e a d t i m e c o n t r o l v s w h g l g h i n p u t t r i - s t a t e l o g i c
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 15 of 27 2.2. thermal warning flag (thwn#) the ZSPM9000 provides a thermal warning flag (thwn#) to indicate over - temperature conditions. the thermal warning flag uses an open - drain output that pulls to cgnd when the activation temperature (150c) is reached. the thwn# output returns to the high - impedance state if the temperature falls to the reset temperature (135c). for use, the thwn# output requires a pull - up resistor, which can be connected to vcin. note that thwn # does not disable the drmos module. figure 2 . 3 thwn # operation 2.3. tri - s tate pwm input the ZSPM9000 incorporates a tri - state 3.3v pwm input gate drive design. the tri - state gate drive has a logic high level, logic low level, and a tri - state shutdown voltage window. when the pw m input signal enters and remains within the tri - state voltage window for a defined hold - off time (t d_hold - off ), both gl and gh are pulled low. this feature enables the gate drive to shut down both high and low side mosfets using only one control signal. for example , this can be used for phase shedding in multi - phase voltage regulators. when exiting a valid tri - state condition, the ZSPM9000 follows the pwm input command. if the pwm input g oes from tri - state to low, the low - side mosfet is turned on. if the pwm input goes from tri - state to high, the high - side mosfet is turned on, as illustrated in figure 2 . 4 . the ZSPM9000 s design allows for short pro pagation delays when exiting the tri - state window (see section 1.3 ). a c t i v a t i o n t e m p e r a t u r e t j _ d r i v e r i c t h e r m a l w a r n i n g n o r m a l o p e r a t i o n h i g h l o w r e s e t t e m p e r a t u r e v o l t a g e a t t h w n # 1 3 5 c 1 5 0 c
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 16 of 27 figure 2 . 4 pwm and tri - s tate timing diagram notes: t pd_xxx = p ropagation delay from extern al signal (pwm, smod, etc.) to ic generated signal; example: t pd_phgll = pwm going high to ls v gs (gl) going low t d_xxx = delay from ic generated signal to ic generated signal; example: t d_deadon = ls v gs low to hs v gs high pwm exiting tri - s tate t pd_ phgll = pwm rise to ls v gs fall, v ih_pwm to 90% ls v gs t pd_tsghh = pwm tri - state to high to hs v gs rise, v ih_pwm to 10% hs v gs t pd_ p l ghl = pwm fall to hs v gs fall, v il_pwm to 90% hs v gs t pd_tsglh = pwm tri - state to low to ls v gs rise, v il_pwm to 10% ls v gs t pd _ phghh = pwm rise to hs v gs rise, v ih_pwm to 10% hs v gs (assumes smod held low) smod (see figure 2 . 5 ) dead times t pd_ slgll = smod fall to ls v gs fall, 90% to 90% ls v gs t d_deadon = ls v gs fall to hs v gs rise, ls - co mp trip value to 10% hs v gs t pd_ shglh = smod rise to ls v gs rise, 10% to 10% ls v gs t d_deadoff = vswh fall to ls v gs rise, sw - comp trip value to 10% ls v gs 2.4. adaptive gate drive circuit the low - side driver (gl) is designed to drive the ground - referenced l ow r ds(on) n - channel mosfet (q2) . the bias for gl is internally connected between vdrv and cgnd. when the driver is enabled, the driver's output is 180 out of phase with the pwm input. when the driver is disabled (disb#=0v), gl is held low. the high - side driver (gh) is designed to drive a floating n - channel mosfet (q1) . the bias voltage for the high - side driver is developed by a bootstrap supply circuit consisting of the internal schottky diode and external bootstrap capacitor (c boot ). during startup, the vswh pin is held at pgnd, allowing c boot (see section 3.2 ) to charge to v drv through the internal diode. when the pwm input goes high, gh begins to charge the gate of the high - side mosfet (q1). during this trans ition, the charge is removed from c boot and delivered to the gate of q1. as q1 turns on, v s wh rises to v in , forcing the boot pin to v i n + v boot , which provides sufficient v gs enhancement for q1. to complete the switching cycle, q1 is turned off by pulling gh to v s wh . c boot is then recharged to v drv when v s wh falls to pgnd. the gh output is in - phase with the pwm input. the high - side gate is held low when the driver is disabled or the pwm signal is held within the tri - state window for longer than the tri - stat e hold - off time, t d_ hold - off (see figure 2 . 4 ) . v s w h g h t o v s w h g l 9 0 % e x i t 3 - s t a t e 1 . 0 v p w m v i l _ p w v i h _ p w m v t r i _ h i v i h _ p w m v i h _ p w m 1 0 % t h o l d - o f f e x i t 3 - s t a t e v i h _ p w m v t r i _ h i v t r i _ l o v d c m t f _ g h s t r _ g h 1 0 % d c m e x i t 3 - s t a t e 9 0 % 1 0 % 9 0 % e n t e r 3 - s t a t e e n t e r 3 - s t a t e e n t e r 3 - s t a t e v i n v o u t 2 . 2 v e n t e r t r i - s t a t e e x i t t r i - s t a t e e n t e r t r i - s t a t e e x i t t r i - s t a t e e x i t t r i - s t a t e e n t e r t r i - s t a t e v i l _ p w m v i l _ p w m t p d _ t s g l h t h o l d - o f f t p d _ t s g h h t h o l d - o f f t p d _ t s g h h c c m t d _ d e a d o f f t d _ d e a d o n t p d _ p h g l l t p d _ p l g h l t f _ g h t f _ g l t r _ g l
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 17 of 27 the driver ic design ensures minimum mosfet dead time while eliminating potential shoot - through (cross - conduction) currents. it senses the state of the mosfets and ad justs the gate drive adaptively to prevent simultaneous conduction. figure 2 . 4 provides the relevant timing waveforms. to prevent overlap during the low - to - high switching transition (q2 off to q1 on), the adaptive circuitry monitors the voltage at the gl pin. when the pwm signal goes high, q2 begins to turn off after a propagation delay (t pd_phgll ). once the gl pin is discharged below ~ 1 v, q1 begins to turn on after adaptive delay t d_deadon . to prevent overlap durin g the high - to - low transition (q1 off to q2 on), the adaptive circuitry monitors the voltage at the vswh pin. when the pwm signal goes low, q1 begins to turn off after a propagation delay (t pd_plghl ). once the vswh pin falls below approx. 2.2v, q2 begins to turn on after adaptive delay t d_deadoff . v gs(q1) is also monitored. when v gs(q1) is discharged below approx. 1.2v, a secondary adaptive delay is initiated that results in q2 being driven on after t d_timeout , regardless of vswh state. this function is impl emented to ensure c boot is recharged each switching cycle in the event that the vswh voltage does not fall below the 2.2v adaptive threshold. secondary delay t d_timeout is longer than t d_deadoff . 2.5. skip mode (smod#) the smod function allows higher converter efficiency under light - load conditions. during smod, the low - side fet gate signal is disabled (held low), preventing discharging of the output capacitors as the filter inductor cur - rent attempts reverse current flow C also known as diode emulation mode . wh en the smod# pin is pulled high, the synchronous buck converter works in synchronous mode. this mode allows gating on the low - side fet. when the smod# pin is pulled low, the low - side fet is gated off. if the smod# pin is connected to the pwm controller, th e controller can actively enable or disable smod when the controller detects light - load operation . table 2 . 2 smod# logic note: the smod feature is intended to have a low propagation delay between the smod sig nal and the low - side fet v gs response time to control diode emulation on a cycle - by - cycle basis . disb# pwm smod# gh gl 0 x x 0 0 1 tri - s tate x 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 18 of 27 figure 2 . 5 smod# timing diagram see figure 2 . 4 for the definitions of the timing parameters. t d _ d e a d o n p w m v s w h g h t o v s w h g l t p d _ p h g l l t p d _ p l g h l t d _ d e a d o f f v i h _ p w m v i l _ p w m 9 0 % 1 0 % 9 0 % 2 . 2 v 2 . 2 v t p d _ p h g h h t p d _ s h g l h d e l a y f r o m s m o d # g o i n g h i g h t o l s v g s h i g h h s t u r n - o n w i t h s m o d # l o w s m o d # t p d _ s l g l l d e l a y f r o m s m o d # g o i n g l o w t o l s v g s l o w d c m c c m c c m 1 0 % v i h _ p w m 1 0 % v o u t v i h _ s m o d v i l _ s m o d 1 0 % v i l _ p w m d e l a y f r o m s m o d # g o i n g l o w t o l s v g s l o w h s t u r n - o n w i t h s m o d # l o w d e l a y f r o m s m o d # g o i n g h i g h t o l s v g s h i g h
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 19 of 27 2.6. pwm figure 2 . 6 pwm timing t d _ d e a d o n p w m v s w h g h t o v s w h g l t p d _ p h g l l t d _ d e a d o f f v i h _ p w m v i l _ p w m 9 0 % 9 0 % 1 . 0 v 1 0 % t p d _ p l g h l 2 . 2 v 1 0 % t d _ t i m e o u t ( 2 5 0 n s t i m e o u t ) 1 . 2 v
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 20 of 27 3 application design 3.1. 5v linear regulator capacitor s election for the linear regulator output (vcin), a local ceramic bypass capacitor is required for linear regulator stability. this capacitor is also needed to reduce noise and is used to supply the peak p ower mosfet low - side gate current and boot capacitor charging current. use at least a 1f capacitor with an x7r or x5r dielectric . keep this capacitor close to the vcin pin and connect it to the cgnd ground plane with vias. a 1f bypass capacitor with an x7r or x5r dielectric is also recommended from vdrv t o c gnd . 3.2. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c boot ), as shown in figure 3 . 1 . a bootstrap capacitance of 100nf using an x7r or x5r capacitor is typically adequate. a series bootst rap resistor may be needed for specific applications to improve switching noise immunity. the boot resistor may be required when operating near the maximum rated v in and is effective at controlling the high - side mosfet turn - on slew rate and v s wh overshoot. typical r boot values from 0.5 to 2.0 are effective in reducing v s wh overshoot. 3.3. power loss and efficiency testing procedures the circuit in figure 3 . 1 has been used to measure power losses. the efficiency has bee n calculated based on the equations below. power loss calculations: (1) (2) (3) (4) (5) efficiency calculations: (6) (7) ? ? out sw sw i v p ? ? ? ? ? ? v 5 v 5 in in in i v i v p ? ? ? ? ? ? out out out i v p ? ? ? ? sw in module _ loss p p p ? ? ? ? out in board _ loss p p p ? ? % p p 100 eff in out board ? ? ? ? ? ? ? ? ? ? % p p 100 eff in sw module ? ? ? ? ? ? ? ? ? ?
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 21 of 27 figure 3 . 1 power loss measurement block diagram v d r v v c i n p w m d i s b # s m o d # p g n d p h a s e v i n b o o t v s w h z s p m 9 0 0 0 t h w n # c g n d c v i n p w m i n p u t v d r v v i n c v d r v c v c i n v o u t c b o o t l o u t a i v d r v o p e n d r a i n o u t p u t d i s b a i i n a i o u t v s w c o u t r b o o t o n o f f v
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 22 of 27 4 pin configuration and package 4.1. available package s the zs pm 9000 is available in a 40 - lead clip - bond pqfn package. the pin - out is shown in figure 4 . 1 . see figure 4 . 2 for the mechanical drawing of the package. figure 4 . 1 pin - out pqfn40 package 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 vswh 43 vin 42 cgnd 41 s m o d # v c i n v d r v b o o t c g n d g h p h a s e n c v i n v i n vin vin vin vin vswh pgnd pgnd pgnd pgnd pgnd v s w h v s w h p g n d p g n d p g n d p g n d p g n d p g n d p g n d p g n d pwm disb # thwn # cgnd gl vswh vswh vswh vswh vswh bottom view 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 vswh 43 vin 42 cgnd 41 s m o d # v c i n v d r v b o o t c g n d g h p h a s e n c v i n v i n vin vin vin vin vswh pgnd pgnd pgnd pgnd pgnd v s w h v s w h p g n d p g n d p g n d p g n d p g n d p g n d p g n d p g n d pwm disb # thwn # cgnd gl vswh vswh vswh vswh vswh top view
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 23 of 27 4.2. pin description pin name description 1 smod# when smod#=high, the low - side driver is the inverse of pwm input. when smod#=low, the low - side driver is disabled. this pin has a 10 a internal pull - up current source. do not add a noise filter capacitor. 2 vcin linear regulator 5v output. minimum 1f x5r/x7r ceramic capacitor to cgnd is requir ed . 3 vdrv linear regulator input. minimum 1f x5r/x7r ceramic capacitor to cgnd is require d. 4 boot bootstrap supply input. provides voltage supply to the high - side mosfet driver. connect a bootstrap capacitor from this pin to phase. 5, 37, 41 cgnd ground return for driver ic. 6 gh gate high. for manufacturing test only. this pin must float: it must not be connected . 7 phase switch node pin for bootstrap capacitor routing; electrically shorted to vswh pin. 8 nc no connect ion . the pin is not el ectrically connected internally but can be connected to vin for convenience. 9 - 14, 42 vin input power voltage (o utput stage supply voltage ) . 15, 29 - 35, 43 vswh switch node. provides return for high - side bootstrapped driver and acts as a sense point for the adaptive shoot - through protection. 16 C 28 pgnd power g round (o utput stage ground ) . source pin of the low - side mosfet. 36 gl gate low. for manufacturing test only. this pin must float. it m ust not be connected . 38 thwn# thermal warning flag, open collector output. when temperature exceeds the trip limit, the output is pulled low. thwn# does no t disable the module. 39 disb# output disable. when low, this pin disables the p ower mos fet switching (gh and gl are held low). this pin has a 10a internal pull - down current source. do not add a noise filter capacitor. 40 pwm pwm signal input. this pin accepts a tri - state 3.3 v pwm signal from the controller.
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 24 of 27 4.3. package dimensions figure 4 . 2 pqfn40 physical dimensions and recommended footprint bottom view land pattern recommendation notes: unless otherwise specified a) does not fully conform to jedec registration mo - 220, dated may/2005. b) all dimensions are in millimeters. c) dimensions do not include burrs or mold flash. mold flash or burrs does not exceed 0.10mm. d) dimensioning and tolerancing per asme y14.5m - 1994. e) drawing file name: pqfn40arev2 see detail 'a' detail 'a' scale: 2:1 seating plane 0.65 0.40 2.10 0.50 typ 4.50 5.80 2.50 0.25 1.60 0. 60 0.15 2.10 0.35 1 top view front view c 0.30 0.20 0. 05 0.00 1.10 0.90 0.10 c 0.08 c 10 11 20 21 30 31 40 0.40 0.50 (0.70) 0.40 2.000.10 2.000.10 (0.20) (0.20) 1.500.10 0.50 0.30 (4 0x) 0.20 6.00 6.00 0.10 c 2x b a 0.10 c 2x 0.30 0.20 (4 0x) 4.400.10 0.10 c a b 0.05 c (2.20) 0.50 10 1 40 31 30 21 20 11 pin#1 indicator pin #1 indicator 2.400.10
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 25 of 27 5 circuit board layout considerations figure 5 . 1 provides an example of a proper layout for the zs p m9000 and critical components. all of the high - current paths, such as vin , vswh , v out , and gnd copper traces , should be short and wide for low inductance and resistance. this techn ique achieves a more stable and evenly distributed current flow with enhanced heat radiation and system performance. the following guidelines are recommendations for the printed circuit board (pcb) designer: 1. input ceramic bypass capacitors must be placed c lose to the vin and pgnd pins. this helps reduce the high - current power loop inductance and the input current ripple induced by the power mosfet switching operation. 2. the vswh copper trace serves two purposes. in addition to being the high - frequency current path from the drmos package to the output inductor, it also serves as a heat sink for the low - side mosfet in the drmos package. the trace should be short and wide enough to present a low - impedance path for the high - frequency, high - current flow between the drmos and inductor to minimize losses and temperature rise. note that the vswh node is a high - voltage and high - frequency switching node with high noise potential. care should be taken to minimize coupling to adjacent traces. since this copper trace also a cts as a heat sink for the lower fet, balance using the largest area possible to improve drmos cooling while maintaining acceptable noise emission. 3. an output inductor should be located close to the ZSPM9000 to minimize the power loss due to the vswh copper trace. care should also be taken so the inductor dissipation does not heat the drmos. 4. the power mosfets used in the output stage are effective at minimizing ringing due to fast switching. in most cases, no vswh snubber is required. if a snubber is used, i t should be placed close to the vswh and pgnd pins. the resistor and capacitor must be the proper size for the power dissipation. 5. vcin, vdrv, and boot capacitors should be placed as close as possible to the respective pins to ensure clean and stable power. routing width and length should be considered as well. 6. include a trace from phase to vswh to improve the noise margin. keep the trace as short as possible. 7. the layout should include a placeholder to insert a small - value series boot resistor (r boot ) betwee n the boot capacitor (c boot ) and drmos boot pin. the boot - to - vswh loop size, including r boot and c boot , should be as small as possible. the boot resistor may be required when operating near the maximum rated v in . the boot resistor is effective at controlli ng the high - side mosfet turn - on slew rate and vswh overshoot. r boot can improve the noise operating margin in synchronous buck designs that might have noise issues due to ground bounce or high positive and negative vswh ringing. however, inserting a boot r esistance lowers the drmos efficiency. efficiency versus noise trade - offs must be considered. r boot values from 0.5 to 2.0 are typically effective in reducing vswh overshoot. 8. the vin and pgnd pins handle large current transients with frequency components greater than 100mhz. if possible, these pins should be connected directly to the vin and board gnd planes. the use of thermal relief traces in series with these pins is discouraged since this adds inductance to the power path. added inductance in series with the vin or pgnd pin degrades system noise immunity by increasing positive and negative vswh rin ging . 9. cgnd pad and pgnd pins should be connected to the gnd plane copper with multiple vias for stable grounding. poor grounding can create a noise transient offset voltage level between cgnd and pgnd. this could lead to faulty operation of the gate driver and mosfets.
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 26 of 27 10. ringing at the boot pin is most effectively controlled by close placement of the boot capacitor. do not add a capacitor from boot to ground ; this may lead to excess current flow through the boot diode. 11. the smod# and disb# pins have weak inter nal pull - up and pull - down current sources, respectively. do not float these pins if avoidable. these pins should not have any noise filter capacitors. 12. use multiple vias on each copper area to interconnect top, inner, and bottom layers to help distribute cu rrent flow and heat conduction. vias should be relatively large and of reasonably low inductance. critical high - frequency components, such as r boot , c boot , the rc snubber, and bypass capacitors should be located as close to the respective drmos module pins as possible on the top layer of the pcb. if this is not feasible, they should be connected from the backside through a network of low - inductance vias. figure 5 . 1 pcb lay out example top view bottom view
zs pm9000 ultra - compact, high - performance drmos device data sheet march 1 2 , 2012 ? 201 2 zentrum mikroelektronik dres den ag rev. 1.01 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 27 of 27 6 ordering informatio n product sales code description package ZSPM9000 a i1r ZSPM9000 lead - free pqfn40 temperature range: - 40c to +125c reel zspm8000 - kit integrated evaluation kit for ZSPM9000 and zspm1000 kit 7 related documents document file name getting started guide: zspm8000 - kit evaluation kit for the zspm1000 single - rail, single - phase true digital pwm controller and the ZSPM9000 drmos zspm8000 - kit-getting started guide_revx_xy.ppt visit zmdis website www.zmdi.com or contact you r nearest sales office for the latest version of these documents. 8 document revision history revision date description 1.00 september 22 , 2011 first release 1. 01 march 1 2 , 2012 minor edits to text and figures . update for zmdi contact information. sales a nd further information www.zmdi.com spm@zmdi.com zentrum mikroelektronik dresden ag grenzstrasse 28 01109 dresden germany zmd america, inc. 1525 mccarthy blvd., #212 milpitas, ca 95 035 - 7453 usa zentrum mikroelektronik dresden ag, japan office 2nd floor, shinbashi tokyu bldg. 4 - 21 - 3, shinbashi, minato - ku tokyo, 105 - 0004 japan zmd far east, ltd. 3f, no. 51, sec. 2, keelung road 11052 taipei taiwan zentrum mikroelektronik dresden ag, k orean office posco centre building west tower, 11th floor 892 daechi, 4 - dong, kangnam - gu seoul, 135 - 777 korea phone +49.351.8822.7.776 fax +49.351.8822.8.7776 phone + 855 - ask - zmdi ( + 855 . 275 . 9634) phone +81.3.6895.7410 fax +81.3.6895.7301 phone +886.2.237 7.8189 fax +886.2.2377.8199 phone +82.2.559.0660 fax +82.2.559.0700 disclaimer : this information applies to a product under development. its characteristics and specifications are subject to change without notice. zentrum mikroelektronik dresden ag (zmd ag) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. the information furnished hereb y is believed to be true and accurate. however, under no circumstances shall zmd ag be liable to any customer, licensee, or any oth er third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. zmd ag hereby expressly d isclaims any liabil ity of zmd ag to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of zmd ag for an y damages in connection with or arising out of the furnishing, performance or use of thi s technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise.
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